1. Field of the Invention
The present invention relates to a flash memory, and more particularly, to a charge trap flash (CTF) memory device and memory card, and system including the same.
2. Description of the Related Art
In general, non-volatile memory devices are semiconductor memory devices in which data stored therein is not erased even if power supply thereto is stopped. Since the non-volatile memory devices have a high data storage capacity, they have been widely employed in mobile communication systems, memory cards, etc.
In the case of a NAND type flash semiconductor memory device, which is an example of a high capacity non-volatile semiconductor memory device being widely used at present, a gate of a transistor thereof has a structure in which a floating gate that stores charges (which represent data) and a control gate controlling the floating gate are sequentially stacked.
To increase the memory capacity, the size of memory cells in flash semiconductor memory devices has been rapidly reduced. Also, a reduction in the height of the floating gate in a vertical direction is required, due to the reduction in the size of the memory cells. Accordingly, in addition to effectively reducing the height of the memory cells in a vertical direction, memory characteristics of a memory cell, for example, retention characteristics for maintaining stored data for a long time, need to be improved. In addition, disturbance between the memory cells, which can be increased as the size of the memory cells is reduced, needs to be prevented.
To solve the problems, a semiconductor memory device that includes a charge trap layer using an insulating material, instead of the floating gate, for storing charges has been suggested. For example, a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) structure or a Metal-Oxide-Nitride-Oxide-Silicon (MONOS) structure, which are each formed of silicon nitride (Si3N4), can be used as the insulating material for storing charges. A charge trap flash (CTF) memory has a structure wherein a threshold voltage shifts when the charges are trapped in the charge trap layer.
The SONOS memory device has a basic structure as follows. A first silicon oxide (SiO2) layer is formed on a semiconductor substrate between a source region and a drain region, and contacts the source region and the drain region. Also, the first silicon oxide layer is a tunnel insulating layer for tunneling charges. A silicon nitride (Si3N4) layer is formed as a charge trap layer on the first silicon oxide layer. The silicon nitride layer is a material layer in which data is stored and charges having tunneled through the first silicon oxide layer are trapped. A second silicon oxide layer operates as a blocking insulating layer formed on the silicon nitride layer to block movement of the charges. A gate electrode is formed on the second silicon oxide layer. In the charge trap flash memory device, in a program operation, electrons are injected and stored in the charge trap layer. In an erasing operation, holes are injected into the charge trap layer, and the electrons stored in the charge trap layer are removed by recombining the holes and the electrons. However, in the SONOS memory device, dielectric constants of a silicon nitride layer and silicon oxide layers are low, and an electron trap site density is not sufficient in the silicon nitride layer and, as such, the SONOS memory device has a high operating voltage and a low program speed. Also, charge retention duration in a vertical or horizontal direction is not sufficient.
An exemplarily charge trap flash memory device according to the prior art will now be described.
FIGS. 1A and 1B are cross-sectional views of a charge trap flash memory device according to the prior art.
Referring to FIG. 1A, a tunnel oxide layer 30, a charge trap layer 40, a blocking insulating layer 50, and a gate electrode 60 are sequentially formed on a substrate 10 in which a source and drain region 20 are formed. In this case, the charge trap layer 40 is formed of silicon nitride and the blocking insulating layer 50 is formed of an aluminum oxide. The gate electrode 60 is formed of a nitrided tantalum. A charge trap flash memory device having such a structure is a MONOS type device described above and in this case is specifically a Thallium-Aluminum oxide-Nitride-Oxide-Silicon (TANOS) structure.
Referring to FIG. 1B, a tunnel oxide layer 30a, a charge trap layer 40a, a blocking insulating layer 50a, and a gate electrode 60a are sequentially formed on a substrate 10a in which a source and drain region 20a are formed. In this case, the charge trap layer 40a is a stack of three layers, that is, a sequential stack of a first silicon nitride layer 42a, a first aluminum oxide layer 44a, and a second silicon nitride layer 46a. The blocking insulating layer 50a is formed of an aluminum oxide and the gate electrode 60a is formed of a nitrided tantalum. A charge trap flash memory device having such a structure is called a Nitride-Aluminum oxide-Nitride (NAN).
FIGS. 2A and 2B illustrate energy band diagrams of the charge trap flash memory devices shown in FIGS. 1A and 1B, respectively.
Referring to FIGS. 2A and 2B, materials used to form the substrates 10 and 10a, the tunnel oxide layers 30 and 30a, the charge trap layers 40 and 40a, the insulating layers 50 and 50a, and the gate electrode 60 and 60a each have their own energy band gaps. A potential barrier exists in interfaces between adjacent structures due to the difference between the energy band gaps.
In the TANOS structure illustrated in FIGS. 1A and 2A, charges are trapped in a deep trap level of the charge trap layer 40 formed of a silicon nitride. Accordingly, a lateral charge spreading, which is a cause of charge loss, is small. On the other hand, the TANOS structure has a high erasing voltage and poor retention characteristics.
In the NAN structure illustrated in FIGS. 1B and 2B, the aluminum oxide layer 44a is interposed between the charge trap layers 42a and 46a formed of a silicon nitride. An erasing voltage and reliability can be improved in the NAN structure, but there is a disadvantage in that it has a low program voltage and high threshold voltage disturbance characteristics.